XX学院
Verilog HDL
乐曲演奏电路设计
专业：动化
学号：
姓名：
设计目求
1课程设计目：
1）加深EDA技术理解掌握乐曲演奏电路工作原理
2）解样控制音调高低变化音长完成乐曲动循环演奏
3）培养学正确分析解决问题力
2课程设计求：
1）Verilog HDL设计乐曲演奏电路系统实现硬件描述语言Verilog HDL分频控制方式进行设计然进行编程时序仿真电路功验证奏出美妙乐曲
2) 通控制输出扬声器激励信号频率高低持续时间扬声器发出连续乐曲声乐曲演奏完成时保证动头开始演奏
3该方案实现功
1)通蜂鸣器播放音乐
2)通三位动态数码输出相应高中低音符
3)通开关实现两首乐曲切换
4)音乐播放时会led流水灯闪烁
应工具介绍
作流行计算机软件系统EDA技术计算机工作台融合应电子技术计算机技术信息处理智化技术新成果进行电子产品动设计EDA提供文输入图形编辑方法设计者意图程序者图形方式表达出常VHDL语言便编写源程序需常见硬件描述语言（HDL）
21 EDA技术介绍
EDA电子设计动化(Electronic Design Automation)缩写20世纪90年代初计算机辅助设计(CAD)计算机辅助制造(CAM)计算机辅助测试(CAT)计算机辅助工程(CAE)概念发展EDA技术电子CAD技术基础发展起计算机软件系统指计算机工作台融合应电子技术计算机技术信息处理智化技术新成果进行电子产品动设计[1]
EDA技术计算机工具设计者EDA软件台硬件描述语言HDL完成设计文件然计算机动完成逻辑编译化简分割综合优化布局布线仿真直特定目标芯片适配编译逻辑映射编程载等工作典型EDA工具中必须包含两特殊软件包综合器适配器综合器功设计者EDA台完成针某系统项目HDL原理图状态图形描述针定硬件系统组件进行编译优化转换综合终获欲实现功描述文件综合器工作前必须定实现硬件结构参数功软件描述定硬件结构定方式联系起说综合器软件描述硬件实现座桥梁综合程电路高级语言描述转换低级目标器件FPGACPLD相映射网表文件
天EDA技术已成电子设计普遍工具设计芯片设计系统没EDA工具支持难完成EDA工具已成设计师必少武器起着越越重作目前EDA技术发展趋势政府重视普应广泛工具样软件功强EDA技术发展迅猛完全日新月异描述EDA技术应广泛现已涉行业EDA水断提高设计工具趋完美步
22 Verilog HDL语言介绍
Verilog HDL种硬件描述语言算法级门级开关级种抽象设计层次数字系统建模建模数字系统象复杂性介简单门完整电子数字系统间数字系统够层次描述相描述中显式进行时序建模[2]
作种通化硬件描述语言Verilog HDL语言具述描述力：设计行特性设计数流特性设计结构组成包含响应监控设计验证方面时延波形产生机制种建模语言外Verilog HDL语言提供编程语言接口通该接口模拟验证期间设计外部访问设计包括模拟具体控制运行[3]
Verilog HDL语言仅定义语法语法结构定义清晰模拟仿真语义种语言编写模型够Verilog仿真器进行验证语言C编程语言中继承种操作符结构Verilog HDL提供扩展建模力中许扩展初难理解Verilog HDL语言核心子集非常易学数建模应说已足够然完整硬件描述语句足复杂芯片完整电子系统进行描述
Verilog HDL语言已成种标准硬件描述语言具特点：
（1）作种途硬件描述语言具易学性易性
（2）Verilog HDL语言允许模块中进行抽象层次描述
（3）数逻辑综合工具支持Verilog HDL成设计员选择
（4）制造厂商提供Verilog HDL工艺库支持仿真
（5）Verilog HDL程序语言接口拥强功允许户C语言部数结构进行描述[3]
正优点Verilog HDL语言广泛流行
面verilog设计流程
Verilog设计流程图
基原理
乐曲演奏原理样：组成乐曲音符频率值（音调）持续时间（音长）乐曲连续演奏需两基数控制输出扬声器激励信号频率高低持续时间扬声器发出连续乐曲声[4]
1 音调控制
频率高低决定音调高低音乐十二均率规定：两8度音（简谱中中音1高音1）间频率相差倍两8度音间分12半音两半音频率12√2 外音名A(简谱中低音6)频率440Hz音名BC间EF间半音余全音[4]计算出简谱中低音1高音1间音名应频率表311示：
表311 简谱中音名频率关系
音名
频率Hz
音名
频率Hz
音名
频率Hz
低音1
2616
中音1
5233
高音1
10465
低音2
2937
中音2
5873
高音2
11747
低音3
3296
中音3
6593
高音3
13185
低音4
3492
中音4
6985
高音4
13969
低音5
392
中音5
784
高音5
1568
低音6
440
中音6
880
高音6
1760
低音7
4939
中音7
9878
高音7
19755
频率信号基准频率分频音阶频率非整数分频系数数必须计算分频数四舍五入取整基准频率低分频太四舍五入取整误差较基准频率高然误差变分频数变实际设计综合考虑两方面素量减频率误差前提取合适基准频率[4]例中选取6MHz基准频率6MHz基准频率先分频6MHz换新基准频率实际音名间相频率关系变演奏出乐曲听起会走调
例需演奏梁祝乐曲该乐曲音阶频率相应分频表2示减输出偶次谐波分量输出扬声器波形应称方波达扬声器前二分频分频器表2中分频6MHz频率二分频3MHz频率基础计算出分频系数9102采14位二进制计数器分频满足需表2中出分频外出应音阶频率时计数器预置数分频系数加载预置数采加载预置数实现分频方法采反馈复零法节省资源实现起容易表312示：
表312 音阶频率应分频预置数
音名
分频
预置数
音名
分频
预置数
低音3
9102
7281
中音2
5111
11272
低音5
7653
8730
中音3
4552
11831
低音6
6818
9565
中音5
3827
12556
低音7
6073
10310
中音6
3409
12974
中音1
5736
10647
高音1
2867
13516
外乐曲中休止符分频系数设0初始值214116383时扬声器会发声
2 音长控制
音符持续时间必须根乐曲速度音符节拍数确定例演奏梁祝片段短音符4分音符果全音符持续时间设1s话需提供4Hz时钟频率产生4分音符时长[4]
图32示乐曲演奏电路原理框图中乐谱产生电路控制音乐音调音长控制音调通设置计数器预置数实现预置数值计数器产生频率信号产生音调控制音长通控制计数器预置数停留时间实现预置数停留时间越长该音符演奏时间越长音符演奏时间025s整数倍节拍较长音符2分音符记谱时该音名连续记录两次
乐曲演奏电路系统框图
音名显示电路显示乐曲演奏时应音符3数码分显示高中低音音名实现演奏动态显示十分直观例中high[30]med[30]low[30]等信号分显示高音中音低音音符演奏循环进行需外设置时长计数器乐曲演奏完成时保证动头开始演奏
方案实现
系统框图方案分成8模块
1）48MHz分频成12MHz波形分频器源代码顶层模块
48mhz分成12mhz分频模块
module div_clk12mhz(clk_48mhzclk_12mhz)
input clk_48mhz
output clk_12mhz
reg clk_12mhz
reg [210] cnt
always @(posedge clk_48mhz)
if(cnt<1) cntcnt+1 (48mhz12mhz4cnt<[4211]）
else begin cnt0 clk_12mhz clk_12mhz end
endmodule
2）12MHz分频成6MHz波形分频器源代码顶层模块：
12mhz分成6mhz分频模块提供song模块
module div_clk6mhz(clk_12mhzclk_6mhz)
input clk_12mhz
output clk_6mhz
reg clk_6mhz
reg cnt
always @(posedge clk_12mhz)
clk_6mhzclk_6mhz
endmodule
3）12MHz分频成4Hz波形分频器源代码顶层模块：
12mhz分成4hz分频模块提供song模块
module div_clk4hz(clk_12mhzclk_4hz)
input clk_12mhz
output clk_4hz
reg clk_4hz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<1499999) cntcnt+1 (12mhz4hz3000000cnt<[3000000211499999]）
else begin cnt0 clk_4hz clk_4hz end
endmodule
4）12MHz分频成1mhz波形分频器源代码顶层模块：
12mhz分成1mhz分频模块提供quma模块
module div_clk1mhz(clk_12mhzclk_1mhz)
input clk_12mhz
output clk_1mhz
reg clk_1mhz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<5) cntcnt+1 (12mhz1mhz12cnt<[12215]）
else begin cnt0 clk_1mhz clk_1mhz end
endmodule
5）12MHz分频成1khz波形分频器源代码顶层模块：
12mhz分成1khz分频模块提供quma模块
module div_clk1khz(clk_12mhzclk_1khz)
input clk_12mhz
output clk_1khz
reg clk_1khz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<5999) cntcnt+1 (12mhz1khz12000cnt<[12000215999]）
else begin cnt0 clk_1khz clk_1khz end
endmodule
6） song模块源代码顶层模块：
音乐产生模块
module song(clk_6mhzclk_4hzspeakerhighmedlowk) 模块名song（端口列表）
input clk_6mhzclk_4hz
input k 定义两输入端口
output speaker 定义输出端口
output[30] highmedlow
reg[30] highmedlow 定义34位寄存器
reg[130] dividerorigin 定义214位寄存器
reg[90] counter 定义110位寄存器
reg speaker
wire carry
assign carry(divider16383) 连续赋值语句
always @(posedge clk_6mhz)
begin if(carry) divider else divider end
always @(posedge carry)
begin speaker<~speakerend 二分频产生方波信号
always @(posedge clk_4hz)
begin
case({highmedlow}) 分频预置
＇b000000000011origin<7281 低音3
＇b000000000101origin<8730 低音5
＇b000000000110origin<9565 低音6
＇b000000000111origin<10310 低音7
＇b000000010000origin<10647 中音1
＇b000000100000origin<11272 中音2
＇b000000110000origin<11831 中音3
＇b000001010000origin<12556 中音5
＇b000001100000origin<12974 中音6
＇b000001110000origin<13347 中音7
＇b000100000000origin<13516 高音1
＇b000000000000origin<16383 休止符
endcase
end
always @(posedge clk_4hz)
if (k0)
begin
if(counter149) counter<0 计时实现循环演奏
else counter case(counter) 记谱
0 {highmedlow}<＇b000000000011 低音3
1 {highmedlow}<＇b000000000011 持续4时钟节拍
2 {highmedlow}<＇b000000000011
3 {highmedlow}<＇b000000000011
4 {highmedlow}<＇b000000000101 低音5
5 {highmedlow}<＇b000000000101 发3时钟节拍
6 {highmedlow}<＇b000000000101
7 {highmedlow}<＇b000000000110 低音6
8 {highmedlow}<＇b000000010000 中音1
9 {highmedlow}<＇b000000010000 发3时钟节拍
10 {highmedlow}<＇b000000010000
11 {highmedlow}<＇b000000100000 中音2
12 {highmedlow}<＇b000000000110 低音6
13 {highmedlow}<＇b000000010000 中音1
14 {highmedlow}<＇b000000000101 低音5
15 {highmedlow}<＇b000000000101
16 {highmedlow}<＇b000001010000 中音5
17 {highmedlow}<＇b000001010000 发3时钟节拍
18 {highmedlow}<＇b000001010000
19 {highmedlow}<＇b000100000000 高音1
20 {highmedlow}<＇b000001100000 中音6
21 {highmedlow}<＇b000001010000 中音5
22 {highmedlow}<＇b000000110000 中音3
23 {highmedlow}<＇b000001010000 中音5
24 {highmedlow}<＇b000000100000 中音2
25 {highmedlow}<＇b000000100000 持续11时钟节拍
26 {highmedlow}<＇b000000100000
27 {highmedlow}<＇b000000100000
28 {highmedlow}<＇b000000100000
29 {highmedlow}<＇b000000100000
30 {highmedlow}<＇b000000100000
31 {highmedlow}<＇b000000100000
32 {highmedlow}<＇b000000100000
33 {highmedlow}<＇b000000100000
34 {highmedlow}<＇b000000100000
35 {highmedlow}<＇b000000110000 中音3
36 {highmedlow}<＇b000000000111 低音7
37 {highmedlow}<＇b000000000111
38 {highmedlow}<＇b000000000110 低音6
39 {highmedlow}<＇b000000000110
40 {highmedlow}<＇b000000000101 低音5
41 {highmedlow}<＇b000000000101
42 {highmedlow}<＇b000000000101
43 {highmedlow}<＇b000000000110 低音6
44 {highmedlow}<＇b000000010000 中音1
45 {highmedlow}<＇b000000010000
46 {highmedlow}<＇b000000100000 中音2
47 {highmedlow}<＇b000000100000
48 {highmedlow}<＇b000000000011 低音3
49 {highmedlow}<＇b000000000011
50 {highmedlow}<＇b000000010000 中音1
51 {highmedlow}<＇b000000010000
52 {highmedlow}<＇b000000000110 低音6
53 {highmedlow}<＇b000000000101 低音5
54 {highmedlow}<＇b000000000110 低音6
55 {highmedlow}<＇b000000010000 中音1
56 {highmedlow}<＇b000000000101 低音5
57 {highmedlow}<＇b000000000101 持续8时钟节拍
58 {highmedlow}<＇b000000000101
59 {highmedlow}<＇b000000000101
60 {highmedlow}<＇b000000000101
61 {highmedlow}<＇b000000000101
62 {highmedlow}<＇b000000000101
63 {highmedlow}<＇b000000000101
64 {highmedlow}<＇b000000110000 中音3
65 {highmedlow}<＇b000000110000 发3时钟节拍
66 {highmedlow}<＇b000000110000
67 {highmedlow}<＇b000001010000 中音5
68 {highmedlow}<＇b000000000111 低音7
69 {highmedlow}<＇b000000000111
70 {highmedlow}<＇b000000100000 中音2
71 {highmedlow}<＇b000000100000
72 {highmedlow}<＇b000000000110 低音6
73 {highmedlow}<＇b000000010000 中音1
74 {highmedlow}<＇b000000000101 低音5
75 {highmedlow}<＇b000000000101 持续4时钟节拍
76 {highmedlow}<＇b000000000101
77 {highmedlow}<＇b000000000101
78 {highmedlow}<＇b000000000000 休止符
79 {highmedlow}<＇b000000000000
80 {highmedlow}<＇b000000000011 低音3
81 {highmedlow}<＇b000000000101 低音5
82 {highmedlow}<＇b000000000101
83 {highmedlow}<＇b000000000011 低音3
84 {highmedlow}<＇b000000000101 低音5
85 {highmedlow}<＇b000000000110 低音6
86 {highmedlow}<＇b000000000111 低音7
87 {highmedlow}<＇b000000100000 中音2
88 {highmedlow}<＇b000000000110 低音6
89 {highmedlow}<＇b000000000110 持续6时钟节拍
90 {highmedlow}<＇b000000000110
91 {highmedlow}<＇b000000000110
92 {highmedlow}<＇b000000000110
93 {highmedlow}<＇b000000000110
94 {highmedlow}<＇b000000000101 低音5
95 {highmedlow}<＇b000000000110 低音6
96 {highmedlow}<＇b000000010000 中音1
97 {highmedlow}<＇b000000010000 发3时钟节拍
98 {highmedlow}<＇b000000010000
99 {highmedlow}<＇b000000100000 中音2
100 {highmedlow}<＇b000001010000 中音5
101 {highmedlow}<＇b000001010000
102 {highmedlow}<＇b000000110000 中音3
103 {highmedlow}<＇b000000110000
104 {highmedlow}<＇b000000100000 中音2
105 {highmedlow}<＇b000000100000
106 {highmedlow}<＇b000000110000 中音3
107 {highmedlow}<＇b000000100000 中音2
108 {highmedlow}<＇b000000010000 中音1
109 {highmedlow}<＇b000000010000
110 {highmedlow}<＇b000000000110 低音6
111 {highmedlow}<＇b000000000101 低音5
112 {highmedlow}<＇b000000000011 低音3
113 {highmedlow}<＇b000000000011 持续4时钟节拍
114 {highmedlow}<＇b000000000011
115 {highmedlow}<＇b000000000011
116 {highmedlow}<＇b000000010000 中音1
117 {highmedlow}<＇b000000010000 持续4时钟节拍
118 {highmedlow}<＇b000000010000
119 {highmedlow}<＇b000000010000
120 {highmedlow}<＇b000000000110 低音6
121 {highmedlow}<＇b000000010000 中音1
122 {highmedlow}<＇b000000000110 低音6
123 {highmedlow}<＇b000000000101 低音5
124 {highmedlow}<＇b000000000011 低音3
125 {highmedlow}<＇b000000000101 低音5
126 {highmedlow}<＇b000000000110 低音6
127 {highmedlow}<＇b000000010000 中音1
128 {highmedlow}<＇b000000000101 低音5
129 {highmedlow}<＇b000000000101 持续6时钟节拍
130 {highmedlow}<＇b000000000101
131 {highmedlow}<＇b000000000101
132 {highmedlow}<＇b000000000101
133 {highmedlow}<＇b000000000101
134 {highmedlow}<＇b000000110000 中音3
135 {highmedlow}<＇b000001010000 中音5
136 {highmedlow}<＇b000000100000 中音2
137 {highmedlow}<＇b000000110000 中音3
138 {highmedlow}<＇b000000100000 中音2
139 {highmedlow}<＇b000000010000 中音1
140 {highmedlow}<＇b000000000111 低音7
141 {highmedlow}<＇b000000000111
142 {highmedlow}<＇b000000000110 低音6
143 {highmedlow}<＇b000000000110
144 {highmedlow}<＇b000000000101 低音5
145 {highmedlow}<＇b000000000101 持续8时钟节拍
146 {highmedlow}<＇b000000000101
147 {highmedlow}<＇b000000000101
148 {highmedlow}<＇b000000000101
149 {highmedlow}<＇b000000000101
endcase
end
else if( k1)
begin
if(counter149) counter<0 计时实现循环演奏
else counter case(counter) 记谱
0 {highmedlow}<＇b000000110000 中音3
1 {highmedlow}<＇b000000110000 持续2时钟节拍
2 {highmedlow}<＇b000000100000 中音2
3 {highmedlow}<＇b000000100000 持续2时钟节拍
4 {highmedlow}<＇b000000110000 中音3
5 {highmedlow}<＇b000000110000 发10时钟节拍
6 {highmedlow}<＇b000000110000
7 {highmedlow}<＇b000000110000
8 {highmedlow}<＇b000000110000
9 {highmedlow}<＇b000000110000
10 {highmedlow}<＇b000000110000
11 {highmedlow}<＇b000000110000
12 {highmedlow}<＇b000000110000
13 {highmedlow}<＇b000000110000
14 {highmedlow}<＇b000000100000 中音2
15 {highmedlow}<＇b000000100000 持续2时钟节拍
16 {highmedlow}<＇b000000110000 中音3
17 {highmedlow}<＇b000000110000 发2时钟节拍
18 {highmedlow}<＇b000000100000 中音2
19 {highmedlow}<＇b000000100000 中音2
20 {highmedlow}<＇b000000010000 中音1
21 {highmedlow}<＇b000000010000
22 {highmedlow}<＇b000000010000
23 {highmedlow}<＇b000000010000
24 {highmedlow}<＇b000000010000
25 {highmedlow}<＇b000000010000
26 {highmedlow}<＇b000000010000
27 {highmedlow}<＇b000000010000
28 {highmedlow}<＇b000000010000
29 {highmedlow}<＇b000000010000
30 {highmedlow}<＇b000000010000
31 {highmedlow}<＇b000000010000
32 {highmedlow}<＇b000000000110低6
33 {highmedlow}<＇b000000000110
34 {highmedlow}<＇b000000010000 中音1
35 {highmedlow}<＇b000000010000
36 {highmedlow}<＇b000000100000 中2 6
37 {highmedlow}<＇b000000100000
38 {highmedlow}<＇b000000100000
39 {highmedlow}<＇b000000100000
40 {highmedlow}<＇b000000100000
41 {highmedlow}<＇b000000100000
42 {highmedlow}<＇b000000110000 中音3
43 {highmedlow}<＇b000000110000
44 {highmedlow}<＇b000000100000 中音2
45 {highmedlow}<＇b000000100000
46 {highmedlow}<＇b000000010000 中音1
47 {highmedlow}<＇b000000010000
48 {highmedlow}<＇b000000000110 低音6
49 {highmedlow}<＇b000000000110
50 {highmedlow}<＇b000000010000 中音1
51 {highmedlow}<＇b000000010000
52 {highmedlow}<＇b000000000101 低音5
53 {highmedlow}<＇b000000000101 低音5
54 {highmedlow}<＇b000000000101
55 {highmedlow}<＇b000000000101
56 {highmedlow}<＇b000000000101 低音5
57 {highmedlow}<＇b000000000101
58 {highmedlow}<＇b000000000101
59 {highmedlow}<＇b000000000101
60 {highmedlow}<＇b000000000101
61 {highmedlow}<＇b000000000101
62 {highmedlow}<＇b000000000101
63 {highmedlow}<＇b000000000101
64 {highmedlow}<＇b000000000101
65 {highmedlow}<＇b000000000101
66 {highmedlow}<＇b000000000101
67 {highmedlow}<＇b000000000101
68 {highmedlow}<＇b000000110000 中音3
69 {highmedlow}<＇b000000110000
70 {highmedlow}<＇b000000100000 中音2
71 {highmedlow}<＇b000000100000
72 {highmedlow}<＇b000000110000 中音3
73 {highmedlow}<＇b000000110000 中音3
74 {highmedlow}<＇b000000110000 中音3
75 {highmedlow}<＇b000000110000 中音3
76 {highmedlow}<＇b000000110000 中音3
77 {highmedlow}<＇b000000110000 中音3
78 {highmedlow}<＇b000000110000 中音3
79 {highmedlow}<＇b000000110000 中音3
80 {highmedlow}<＇b000000110000 中音3
81 {highmedlow}<＇b000000110000 中音3
82 {highmedlow}<＇b000000100000 中音2
83 {highmedlow}<＇b000000100000
84 {highmedlow}<＇b000000110000 中音3
85 {highmedlow}<＇b000000110000 中音3
86 {highmedlow}<＇b000000100000 中音2
87 {highmedlow}<＇b000000100000 中音2
88 {highmedlow}<＇b000000010000 中音1
89 {highmedlow}<＇b000000010000 中音1
90 {highmedlow}<＇b000000010000 中音1
91 {highmedlow}<＇b000000010000 中音1
92 {highmedlow}<＇b000000010000 中音1
93 {highmedlow}<＇b000000010000 中音1
94 {highmedlow}<＇b000000010000 中音1
95 {highmedlow}<＇b000000010000 中音1
96 {highmedlow}<＇b000000010000 中音1
97 {highmedlow}<＇b000000010000 中音1
98 {highmedlow}<＇b000000010000 中音1
99 {highmedlow}<＇b000000010000 中音1
100 {highmedlow}<＇b000000010000 中音1
101 {highmedlow}<＇b000000010000 中音1
102 {highmedlow}<＇b000000010000 中音1
103 {highmedlow}<＇b000000010000 中音1
104 {highmedlow}<＇b000000010000 中音1
105 {highmedlow}<＇b000000000110 低音6
106 {highmedlow}<＇b000000000110 低音6
107 {highmedlow}<＇b000000010000 中音1
108 {highmedlow}<＇b000000010000 中音1
109 {highmedlow}<＇b000000100000 中音2
110 {highmedlow}<＇b000000100000 中音2
111 {highmedlow}<＇b000000100000 中音2
112 {highmedlow}<＇b000000100000 中音2
113 {highmedlow}<＇b000000100000 中音2
114 {highmedlow}<＇b000000100000 中音2
115 {highmedlow}<＇b000000110000 中音3
116 {highmedlow}<＇b000000110000
117 {highmedlow}<＇b000000100000 中音2
118 {highmedlow}<＇b000000100000
119 {highmedlow}<＇b000000010000 中音1
120 {highmedlow}<＇b000000010000
121 {highmedlow}<＇b000000000110 低音6
122 {highmedlow}<＇b000000000110
123 {highmedlow}<＇b000000010000 中音1
124 {highmedlow}<＇b000000010000
125 {highmedlow}<＇b000000100000 中音2
126 {highmedlow}<＇b000000100000 中音2
127 {highmedlow}<＇b000000100000 中音2
128 {highmedlow}<＇b000000100000 中音2
129 {highmedlow}<＇b000000100000 中音2
130 {highmedlow}<＇b000000100000 中音2
131 {highmedlow}<＇b000000100000 中音2
132 {highmedlow}<＇b000000100000 中音2
133 {highmedlow}<＇b000000100000 中音2
134 {highmedlow}<＇b000000100000 中音2
135 {highmedlow}<＇b000000100000 中音2
136 {highmedlow}<＇b000000100000 中音2
137 {highmedlow}<＇b000000100000 中音2
138 {highmedlow}<＇b000000100000 中音2
139 {highmedlow}<＇b000000100000 中音2
140 {highmedlow}<＇b000000100000 中音2
141 {highmedlow}<＇b000000110000 中音3
142 {highmedlow}<＇b000000110000 持续2时钟节拍
143 {highmedlow}<＇b000000100000 中音2
144 {highmedlow}<＇b000000100000 持续2时钟节拍
145 {highmedlow}<＇b000000110000 中音3
146 {highmedlow}<＇b000000110000 发10时钟节拍
147 {highmedlow}<＇b000000110000
148 {highmedlow}<＇b000000110000
149 {highmedlow}<＇b000000110000
endcase
end
endmodule 模块结束
7）取码模块源代码顶层模块：
取码模块song模块取数码显示部分位码段码
module quma(highmedlowclk_1mhzdigduan)
input [30] highmedlow
input clk_1mhz
reg[70] dig
output [70]dig定义输出八位位码
reg [70] duan
output [70] duan 定义输出段码代码
always @(posedge clk_1mhz)扫描highmedlow三寄存器值取出位码段码代码
begin
if (high0) 果high值0输出high值
begin dig<8＇b11111011
case (high)
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
else if (med0) 果med值0输出med值
begin dig<8＇b11111101
case (med )
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
else if (low0) 果low值0输出low值
begin dig<8＇b11111110
case (low )
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
end
endmodule
8）disp：显示模块位输出转换七段数码显示源代码顶层模块：
动态数码显示模块
module disp(duanclk_1khzseg)
input [70]duan
input clk_1khz
output [70]seg
reg [70]seg
always @(posedge clk_1khz)
begin
case(duan)
1seg8＇b11111001
2seg8＇b10100100
3seg8＇b10110000
4seg8＇b10011001
5seg8＇b10010010
6seg8＇b10000010
7seg8＇b11111000
default seg8＇b11111001
endcase
end
endmodule
方案测试
顶层图形文件建立系统进行仿真仿真时输入输出信号频率求先模块进行仿真
1） 48MHz分频成12MHz波形模块仿真波形：
2） 12MHz分频成6MHz波形模块仿真波形：
3）12MHz分频成1MHz波形模块仿真波形：
4）12MHz分频成4Hz波形模块仿真波形：
5）12MHz分频成1khz波形模块仿真波形：
6）音乐发生器模块仿真波形：
7）取码模块仿真波形：
8）显示模块仿真波形：
引脚锁定：
功模块波形仿真通画出原理图仿真完毕接开始引脚锁定：引脚锁定列表表示：
端口名称
引脚位置
端口名称
引脚位置
clk_48mhz
N2
Dig[7]
M4
Speaker
F18
Seg[0]
J8
Dig[0]
L6
Seg[1]
M3
Dig[1]
K5
Seg[2]
K6
Dig[2]
G3
Seg[3]
J6
Dig[3]
G4
Seg[4]
U10
Dig[4]
J3
Seg[5]
N9
Dig[5]
K4
Seg[6]
L10
Dig[6]
L3
Seg[7]
L9
k
L25
引脚锁定载程序：
安装usbblaster驱动程序配置JTAG文件载程序试验箱FPGA芯片中进行调试仿真修改直预期仿真结果
附录：乐曲演奏电路设计原理图生成顶层文件
原理图生成文文件源程序
Copyright (C) 19912006 Altera Corporation
Your Use Of Altera Corporation＇s Design Tools Logic Functions
And Other Software And Tools And Its Ampp Partner Logic
Functions And Any Output Files Any Of The Foregoing
(Including Device Programming Or Simulation Files) And Any
Associated Documentation Or Information Are Expressly Subject
To The Terms And Conditions Of The Altera Program License
Subscription Agreement Altera Megacore Function License
Agreement Or Other Applicable License Agreement Including
Without Limitation That Your Use Is For The Sole Purpose Of
Programming Logic Devices Manufactured By Altera And Sold By
Altera Or Its Authorized Distributors Please Refer To The
Applicable Agreement For Further Details
Module Block1(
Clk_48mhz
Speaker
Dig
Seg
)
Input Clk_48mhz
Output Speaker
Output [70] Dig
Output [70] Seg
Wire Synthesized_Wire_12
Wire Synthesized_Wire_4
Wire [60] Synthesized_Wire_5
Wire Synthesized_Wire_6
Wire Synthesized_Wire_7
Wire Synthesized_Wire_8
Wire [30] Synthesized_Wire_9
Wire [30] Synthesized_Wire_10
Wire [30] Synthesized_Wire_11
Div_Clk12mhz B2v_Inst(Clk_48mhz(Clk_48mhz)
Clk_12mhz(Synthesized_Wire_12))
Div_Clk1khz B2v_Inst1(Clk_12mhz(Synthesized_Wire_12)
Clk_1khz(Synthesized_Wire_4))
Div_Clk1mhz B2v_Inst2(Clk_12mhz(Synthesized_Wire_12)
Clk_1mhz(Synthesized_Wire_8))
Div_Clk4hz B2v_Inst3(Clk_12mhz(Synthesized_Wire_12)
Clk_4hz(Synthesized_Wire_7))
Div_Clk6mhz B2v_Inst4(Clk_12mhz(Synthesized_Wire_12)
Clk_6mhz(Synthesized_Wire_6))
Disp B2v_Inst5(Clk_1khz(Synthesized_Wire_4)
Duan(Synthesized_Wire_5)Seg(Seg))
Song B2v_Inst6(Clk_6mhz(Synthesized_Wire_6)
Clk_4hz(Synthesized_Wire_7)Speaker(Speaker)High(Synthesized_Wire_9)Low(Synthesized_Wire_10)Med(Synthesized_Wire_11))
Quma B2v_Inst9(Clk_1mhz(Synthesized_Wire_8)
High(Synthesized_Wire_9)Low(Synthesized_Wire_10)Med(Synthesized_Wire_11)Dig(Dig)Duan(Synthesized_Wire_5))
Endmodule
实训心
2周实训深刻体会知识匮乏原学理知识通次实理知识升实践程时实践中加深理知识理解外次实仅verilog提高 学许方面知识提高动手力
次实训中遇少问题中12mhz分频4hz时候仿真波形仿真出步步分析发现原设置endtime时间太长想仿真出波形便观察设置10s结果仿真百分49然仿真动调试设置05秒样十分钟仿真仿真波形调试出次编程时候程序综合出现错误song模块中阻塞非阻塞赋值时出现程序中显示模块中开始编写七位二进制阴数码结果硬件测试时候数码显示正常发现数点没赋值数码阳调试修改程序成功高中低音调音节显示出次想编译2首歌switch切换演唱歌曲时组成员研究歌谱例子进行午写出两蝴蝶程序修改song程序成功进行仿真点阵显示歌名时候发现芯片点阵输出引脚3老师分析讲解学会新程序an
通次实仅学知识新认识提高考虑问题分析问题全面性动手操作力培养团队合作精神学致意识做事情规范认真态度综合力提高总课程设计学新知识巩固加深学课理知识程培养综合运知识力思考解决问题力仅加深电子技术课程理解感受设计电路乐趣怕麻烦反复设计绘图修改希次课程设计做说次课程设计非常意义
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XX学院
Verilog HDL
乐曲演奏电路设计
专业：动化
学号：
姓名：
设计目求
1课程设计目：
1）加深EDA技术理解掌握乐曲演奏电路工作原理
2）解样控制音调高低变化音长完成乐曲动循环演奏
3）培养学正确分析解决问题力
2课程设计求：
1）Verilog HDL设计乐曲演奏电路系统实现硬件描述语言Verilog HDL分频控制方式进行设计然进行编程时序仿真电路功验证奏出美妙乐曲
2) 通控制输出扬声器激励信号频率高低持续时间扬声器发出连续乐曲声乐曲演奏完成时保证动头开始演奏
3该方案实现功
1)通蜂鸣器播放音乐
2)通三位动态数码输出相应高中低音符
3)通开关实现两首乐曲切换
4)音乐播放时会led流水灯闪烁
应工具介绍
作流行计算机软件系统EDA技术计算机工作台融合应电子技术计算机技术信息处理智化技术新成果进行电子产品动设计EDA提供文输入图形编辑方法设计者意图程序者图形方式表达出常VHDL语言便编写源程序需常见硬件描述语言（HDL）
21 EDA技术介绍
EDA电子设计动化(Electronic Design Automation)缩写20世纪90年代初计算机辅助设计(CAD)计算机辅助制造(CAM)计算机辅助测试(CAT)计算机辅助工程(CAE)概念发展EDA技术电子CAD技术基础发展起计算机软件系统指计算机工作台融合应电子技术计算机技术信息处理智化技术新成果进行电子产品动设计[1]
EDA技术计算机工具设计者EDA软件台硬件描述语言HDL完成设计文件然计算机动完成逻辑编译化简分割综合优化布局布线仿真直特定目标芯片适配编译逻辑映射编程载等工作典型EDA工具中必须包含两特殊软件包综合器适配器综合器功设计者EDA台完成针某系统项目HDL原理图状态图形描述针定硬件系统组件进行编译优化转换综合终获欲实现功描述文件综合器工作前必须定实现硬件结构参数功软件描述定硬件结构定方式联系起说综合器软件描述硬件实现座桥梁综合程电路高级语言描述转换低级目标器件FPGACPLD相映射网表文件
天EDA技术已成电子设计普遍工具设计芯片设计系统没EDA工具支持难完成EDA工具已成设计师必少武器起着越越重作目前EDA技术发展趋势政府重视普应广泛工具样软件功强EDA技术发展迅猛完全日新月异描述EDA技术应广泛现已涉行业EDA水断提高设计工具趋完美步
22 Verilog HDL语言介绍
Verilog HDL种硬件描述语言算法级门级开关级种抽象设计层次数字系统建模建模数字系统象复杂性介简单门完整电子数字系统间数字系统够层次描述相描述中显式进行时序建模[2]
作种通化硬件描述语言Verilog HDL语言具述描述力：设计行特性设计数流特性设计结构组成包含响应监控设计验证方面时延波形产生机制种建模语言外Verilog HDL语言提供编程语言接口通该接口模拟验证期间设计外部访问设计包括模拟具体控制运行[3]
Verilog HDL语言仅定义语法语法结构定义清晰模拟仿真语义种语言编写模型够Verilog仿真器进行验证语言C编程语言中继承种操作符结构Verilog HDL提供扩展建模力中许扩展初难理解Verilog HDL语言核心子集非常易学数建模应说已足够然完整硬件描述语句足复杂芯片完整电子系统进行描述
Verilog HDL语言已成种标准硬件描述语言具特点：
（1）作种途硬件描述语言具易学性易性
（2）Verilog HDL语言允许模块中进行抽象层次描述
（3）数逻辑综合工具支持Verilog HDL成设计员选择
（4）制造厂商提供Verilog HDL工艺库支持仿真
（5）Verilog HDL程序语言接口拥强功允许户C语言部数结构进行描述[3]
正优点Verilog HDL语言广泛流行
面verilog设计流程
Verilog设计流程图
基原理
乐曲演奏原理样：组成乐曲音符频率值（音调）持续时间（音长）乐曲连续演奏需两基数控制输出扬声器激励信号频率高低持续时间扬声器发出连续乐曲声[4]
1 音调控制
频率高低决定音调高低音乐十二均率规定：两8度音（简谱中中音1高音1）间频率相差倍两8度音间分12半音两半音频率12√2 外音名A(简谱中低音6)频率440Hz音名BC间EF间半音余全音[4]计算出简谱中低音1高音1间音名应频率表311示：
表311 简谱中音名频率关系
音名
频率Hz
音名
频率Hz
音名
频率Hz
低音1
2616
中音1
5233
高音1
10465
低音2
2937
中音2
5873
高音2
11747
低音3
3296
中音3
6593
高音3
13185
低音4
3492
中音4
6985
高音4
13969
低音5
392
中音5
784
高音5
1568
低音6
440
中音6
880
高音6
1760
低音7
4939
中音7
9878
高音7
19755
频率信号基准频率分频音阶频率非整数分频系数数必须计算分频数四舍五入取整基准频率低分频太四舍五入取整误差较基准频率高然误差变分频数变实际设计综合考虑两方面素量减频率误差前提取合适基准频率[4]例中选取6MHz基准频率6MHz基准频率先分频6MHz换新基准频率实际音名间相频率关系变演奏出乐曲听起会走调
例需演奏梁祝乐曲该乐曲音阶频率相应分频表2示减输出偶次谐波分量输出扬声器波形应称方波达扬声器前二分频分频器表2中分频6MHz频率二分频3MHz频率基础计算出分频系数9102采14位二进制计数器分频满足需表2中出分频外出应音阶频率时计数器预置数分频系数加载预置数采加载预置数实现分频方法采反馈复零法节省资源实现起容易表312示：
表312 音阶频率应分频预置数
音名
分频
预置数
音名
分频
预置数
低音3
9102
7281
中音2
5111
11272
低音5
7653
8730
中音3
4552
11831
低音6
6818
9565
中音5
3827
12556
低音7
6073
10310
中音6
3409
12974
中音1
5736
10647
高音1
2867
13516
外乐曲中休止符分频系数设0初始值214116383时扬声器会发声
2 音长控制
音符持续时间必须根乐曲速度音符节拍数确定例演奏梁祝片段短音符4分音符果全音符持续时间设1s话需提供4Hz时钟频率产生4分音符时长[4]
图32示乐曲演奏电路原理框图中乐谱产生电路控制音乐音调音长控制音调通设置计数器预置数实现预置数值计数器产生频率信号产生音调控制音长通控制计数器预置数停留时间实现预置数停留时间越长该音符演奏时间越长音符演奏时间025s整数倍节拍较长音符2分音符记谱时该音名连续记录两次
乐曲演奏电路系统框图
音名显示电路显示乐曲演奏时应音符3数码分显示高中低音音名实现演奏动态显示十分直观例中high[30]med[30]low[30]等信号分显示高音中音低音音符演奏循环进行需外设置时长计数器乐曲演奏完成时保证动头开始演奏
方案实现
系统框图方案分成8模块
1）48MHz分频成12MHz波形分频器源代码顶层模块
48mhz分成12mhz分频模块
module div_clk12mhz(clk_48mhzclk_12mhz)
input clk_48mhz
output clk_12mhz
reg clk_12mhz
reg [210] cnt
always @(posedge clk_48mhz)
if(cnt<1) cntcnt+1 (48mhz12mhz4cnt<[4211]）
else begin cnt0 clk_12mhz clk_12mhz end
endmodule
2）12MHz分频成6MHz波形分频器源代码顶层模块：
12mhz分成6mhz分频模块提供song模块
module div_clk6mhz(clk_12mhzclk_6mhz)
input clk_12mhz
output clk_6mhz
reg clk_6mhz
reg cnt
always @(posedge clk_12mhz)
clk_6mhzclk_6mhz
endmodule
3）12MHz分频成4Hz波形分频器源代码顶层模块：
12mhz分成4hz分频模块提供song模块
module div_clk4hz(clk_12mhzclk_4hz)
input clk_12mhz
output clk_4hz
reg clk_4hz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<1499999) cntcnt+1 (12mhz4hz3000000cnt<[3000000211499999]）
else begin cnt0 clk_4hz clk_4hz end
endmodule
4）12MHz分频成1mhz波形分频器源代码顶层模块：
12mhz分成1mhz分频模块提供quma模块
module div_clk1mhz(clk_12mhzclk_1mhz)
input clk_12mhz
output clk_1mhz
reg clk_1mhz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<5) cntcnt+1 (12mhz1mhz12cnt<[12215]）
else begin cnt0 clk_1mhz clk_1mhz end
endmodule
5）12MHz分频成1khz波形分频器源代码顶层模块：
12mhz分成1khz分频模块提供quma模块
module div_clk1khz(clk_12mhzclk_1khz)
input clk_12mhz
output clk_1khz
reg clk_1khz
reg [210] cnt
always @(posedge clk_12mhz)
if(cnt<5999) cntcnt+1 (12mhz1khz12000cnt<[12000215999]）
else begin cnt0 clk_1khz clk_1khz end
endmodule
6） song模块源代码顶层模块：
音乐产生模块
module song(clk_6mhzclk_4hzspeakerhighmedlowk) 模块名song（端口列表）
input clk_6mhzclk_4hz
input k 定义两输入端口
output speaker 定义输出端口
output[30] highmedlow
reg[30] highmedlow 定义34位寄存器
reg[130] dividerorigin 定义214位寄存器
reg[90] counter 定义110位寄存器
reg speaker
wire carry
assign carry(divider16383) 连续赋值语句
always @(posedge clk_6mhz)
begin if(carry) divider
always @(posedge carry)
begin speaker<~speakerend 二分频产生方波信号
always @(posedge clk_4hz)
begin
case({highmedlow}) 分频预置
＇b000000000011origin<7281 低音3
＇b000000000101origin<8730 低音5
＇b000000000110origin<9565 低音6
＇b000000000111origin<10310 低音7
＇b000000010000origin<10647 中音1
＇b000000100000origin<11272 中音2
＇b000000110000origin<11831 中音3
＇b000001010000origin<12556 中音5
＇b000001100000origin<12974 中音6
＇b000001110000origin<13347 中音7
＇b000100000000origin<13516 高音1
＇b000000000000origin<16383 休止符
endcase
end
always @(posedge clk_4hz)
if (k0)
begin
if(counter149) counter<0 计时实现循环演奏
else counter
0 {highmedlow}<＇b000000000011 低音3
1 {highmedlow}<＇b000000000011 持续4时钟节拍
2 {highmedlow}<＇b000000000011
3 {highmedlow}<＇b000000000011
4 {highmedlow}<＇b000000000101 低音5
5 {highmedlow}<＇b000000000101 发3时钟节拍
6 {highmedlow}<＇b000000000101
7 {highmedlow}<＇b000000000110 低音6
8 {highmedlow}<＇b000000010000 中音1
9 {highmedlow}<＇b000000010000 发3时钟节拍
10 {highmedlow}<＇b000000010000
11 {highmedlow}<＇b000000100000 中音2
12 {highmedlow}<＇b000000000110 低音6
13 {highmedlow}<＇b000000010000 中音1
14 {highmedlow}<＇b000000000101 低音5
15 {highmedlow}<＇b000000000101
16 {highmedlow}<＇b000001010000 中音5
17 {highmedlow}<＇b000001010000 发3时钟节拍
18 {highmedlow}<＇b000001010000
19 {highmedlow}<＇b000100000000 高音1
20 {highmedlow}<＇b000001100000 中音6
21 {highmedlow}<＇b000001010000 中音5
22 {highmedlow}<＇b000000110000 中音3
23 {highmedlow}<＇b000001010000 中音5
24 {highmedlow}<＇b000000100000 中音2
25 {highmedlow}<＇b000000100000 持续11时钟节拍
26 {highmedlow}<＇b000000100000
27 {highmedlow}<＇b000000100000
28 {highmedlow}<＇b000000100000
29 {highmedlow}<＇b000000100000
30 {highmedlow}<＇b000000100000
31 {highmedlow}<＇b000000100000
32 {highmedlow}<＇b000000100000
33 {highmedlow}<＇b000000100000
34 {highmedlow}<＇b000000100000
35 {highmedlow}<＇b000000110000 中音3
36 {highmedlow}<＇b000000000111 低音7
37 {highmedlow}<＇b000000000111
38 {highmedlow}<＇b000000000110 低音6
39 {highmedlow}<＇b000000000110
40 {highmedlow}<＇b000000000101 低音5
41 {highmedlow}<＇b000000000101
42 {highmedlow}<＇b000000000101
43 {highmedlow}<＇b000000000110 低音6
44 {highmedlow}<＇b000000010000 中音1
45 {highmedlow}<＇b000000010000
46 {highmedlow}<＇b000000100000 中音2
47 {highmedlow}<＇b000000100000
48 {highmedlow}<＇b000000000011 低音3
49 {highmedlow}<＇b000000000011
50 {highmedlow}<＇b000000010000 中音1
51 {highmedlow}<＇b000000010000
52 {highmedlow}<＇b000000000110 低音6
53 {highmedlow}<＇b000000000101 低音5
54 {highmedlow}<＇b000000000110 低音6
55 {highmedlow}<＇b000000010000 中音1
56 {highmedlow}<＇b000000000101 低音5
57 {highmedlow}<＇b000000000101 持续8时钟节拍
58 {highmedlow}<＇b000000000101
59 {highmedlow}<＇b000000000101
60 {highmedlow}<＇b000000000101
61 {highmedlow}<＇b000000000101
62 {highmedlow}<＇b000000000101
63 {highmedlow}<＇b000000000101
64 {highmedlow}<＇b000000110000 中音3
65 {highmedlow}<＇b000000110000 发3时钟节拍
66 {highmedlow}<＇b000000110000
67 {highmedlow}<＇b000001010000 中音5
68 {highmedlow}<＇b000000000111 低音7
69 {highmedlow}<＇b000000000111
70 {highmedlow}<＇b000000100000 中音2
71 {highmedlow}<＇b000000100000
72 {highmedlow}<＇b000000000110 低音6
73 {highmedlow}<＇b000000010000 中音1
74 {highmedlow}<＇b000000000101 低音5
75 {highmedlow}<＇b000000000101 持续4时钟节拍
76 {highmedlow}<＇b000000000101
77 {highmedlow}<＇b000000000101
78 {highmedlow}<＇b000000000000 休止符
79 {highmedlow}<＇b000000000000
80 {highmedlow}<＇b000000000011 低音3
81 {highmedlow}<＇b000000000101 低音5
82 {highmedlow}<＇b000000000101
83 {highmedlow}<＇b000000000011 低音3
84 {highmedlow}<＇b000000000101 低音5
85 {highmedlow}<＇b000000000110 低音6
86 {highmedlow}<＇b000000000111 低音7
87 {highmedlow}<＇b000000100000 中音2
88 {highmedlow}<＇b000000000110 低音6
89 {highmedlow}<＇b000000000110 持续6时钟节拍
90 {highmedlow}<＇b000000000110
91 {highmedlow}<＇b000000000110
92 {highmedlow}<＇b000000000110
93 {highmedlow}<＇b000000000110
94 {highmedlow}<＇b000000000101 低音5
95 {highmedlow}<＇b000000000110 低音6
96 {highmedlow}<＇b000000010000 中音1
97 {highmedlow}<＇b000000010000 发3时钟节拍
98 {highmedlow}<＇b000000010000
99 {highmedlow}<＇b000000100000 中音2
100 {highmedlow}<＇b000001010000 中音5
101 {highmedlow}<＇b000001010000
102 {highmedlow}<＇b000000110000 中音3
103 {highmedlow}<＇b000000110000
104 {highmedlow}<＇b000000100000 中音2
105 {highmedlow}<＇b000000100000
106 {highmedlow}<＇b000000110000 中音3
107 {highmedlow}<＇b000000100000 中音2
108 {highmedlow}<＇b000000010000 中音1
109 {highmedlow}<＇b000000010000
110 {highmedlow}<＇b000000000110 低音6
111 {highmedlow}<＇b000000000101 低音5
112 {highmedlow}<＇b000000000011 低音3
113 {highmedlow}<＇b000000000011 持续4时钟节拍
114 {highmedlow}<＇b000000000011
115 {highmedlow}<＇b000000000011
116 {highmedlow}<＇b000000010000 中音1
117 {highmedlow}<＇b000000010000 持续4时钟节拍
118 {highmedlow}<＇b000000010000
119 {highmedlow}<＇b000000010000
120 {highmedlow}<＇b000000000110 低音6
121 {highmedlow}<＇b000000010000 中音1
122 {highmedlow}<＇b000000000110 低音6
123 {highmedlow}<＇b000000000101 低音5
124 {highmedlow}<＇b000000000011 低音3
125 {highmedlow}<＇b000000000101 低音5
126 {highmedlow}<＇b000000000110 低音6
127 {highmedlow}<＇b000000010000 中音1
128 {highmedlow}<＇b000000000101 低音5
129 {highmedlow}<＇b000000000101 持续6时钟节拍
130 {highmedlow}<＇b000000000101
131 {highmedlow}<＇b000000000101
132 {highmedlow}<＇b000000000101
133 {highmedlow}<＇b000000000101
134 {highmedlow}<＇b000000110000 中音3
135 {highmedlow}<＇b000001010000 中音5
136 {highmedlow}<＇b000000100000 中音2
137 {highmedlow}<＇b000000110000 中音3
138 {highmedlow}<＇b000000100000 中音2
139 {highmedlow}<＇b000000010000 中音1
140 {highmedlow}<＇b000000000111 低音7
141 {highmedlow}<＇b000000000111
142 {highmedlow}<＇b000000000110 低音6
143 {highmedlow}<＇b000000000110
144 {highmedlow}<＇b000000000101 低音5
145 {highmedlow}<＇b000000000101 持续8时钟节拍
146 {highmedlow}<＇b000000000101
147 {highmedlow}<＇b000000000101
148 {highmedlow}<＇b000000000101
149 {highmedlow}<＇b000000000101
endcase
end
else if( k1)
begin
if(counter149) counter<0 计时实现循环演奏
else counter
0 {highmedlow}<＇b000000110000 中音3
1 {highmedlow}<＇b000000110000 持续2时钟节拍
2 {highmedlow}<＇b000000100000 中音2
3 {highmedlow}<＇b000000100000 持续2时钟节拍
4 {highmedlow}<＇b000000110000 中音3
5 {highmedlow}<＇b000000110000 发10时钟节拍
6 {highmedlow}<＇b000000110000
7 {highmedlow}<＇b000000110000
8 {highmedlow}<＇b000000110000
9 {highmedlow}<＇b000000110000
10 {highmedlow}<＇b000000110000
11 {highmedlow}<＇b000000110000
12 {highmedlow}<＇b000000110000
13 {highmedlow}<＇b000000110000
14 {highmedlow}<＇b000000100000 中音2
15 {highmedlow}<＇b000000100000 持续2时钟节拍
16 {highmedlow}<＇b000000110000 中音3
17 {highmedlow}<＇b000000110000 发2时钟节拍
18 {highmedlow}<＇b000000100000 中音2
19 {highmedlow}<＇b000000100000 中音2
20 {highmedlow}<＇b000000010000 中音1
21 {highmedlow}<＇b000000010000
22 {highmedlow}<＇b000000010000
23 {highmedlow}<＇b000000010000
24 {highmedlow}<＇b000000010000
25 {highmedlow}<＇b000000010000
26 {highmedlow}<＇b000000010000
27 {highmedlow}<＇b000000010000
28 {highmedlow}<＇b000000010000
29 {highmedlow}<＇b000000010000
30 {highmedlow}<＇b000000010000
31 {highmedlow}<＇b000000010000
32 {highmedlow}<＇b000000000110低6
33 {highmedlow}<＇b000000000110
34 {highmedlow}<＇b000000010000 中音1
35 {highmedlow}<＇b000000010000
36 {highmedlow}<＇b000000100000 中2 6
37 {highmedlow}<＇b000000100000
38 {highmedlow}<＇b000000100000
39 {highmedlow}<＇b000000100000
40 {highmedlow}<＇b000000100000
41 {highmedlow}<＇b000000100000
42 {highmedlow}<＇b000000110000 中音3
43 {highmedlow}<＇b000000110000
44 {highmedlow}<＇b000000100000 中音2
45 {highmedlow}<＇b000000100000
46 {highmedlow}<＇b000000010000 中音1
47 {highmedlow}<＇b000000010000
48 {highmedlow}<＇b000000000110 低音6
49 {highmedlow}<＇b000000000110
50 {highmedlow}<＇b000000010000 中音1
51 {highmedlow}<＇b000000010000
52 {highmedlow}<＇b000000000101 低音5
53 {highmedlow}<＇b000000000101 低音5
54 {highmedlow}<＇b000000000101
55 {highmedlow}<＇b000000000101
56 {highmedlow}<＇b000000000101 低音5
57 {highmedlow}<＇b000000000101
58 {highmedlow}<＇b000000000101
59 {highmedlow}<＇b000000000101
60 {highmedlow}<＇b000000000101
61 {highmedlow}<＇b000000000101
62 {highmedlow}<＇b000000000101
63 {highmedlow}<＇b000000000101
64 {highmedlow}<＇b000000000101
65 {highmedlow}<＇b000000000101
66 {highmedlow}<＇b000000000101
67 {highmedlow}<＇b000000000101
68 {highmedlow}<＇b000000110000 中音3
69 {highmedlow}<＇b000000110000
70 {highmedlow}<＇b000000100000 中音2
71 {highmedlow}<＇b000000100000
72 {highmedlow}<＇b000000110000 中音3
73 {highmedlow}<＇b000000110000 中音3
74 {highmedlow}<＇b000000110000 中音3
75 {highmedlow}<＇b000000110000 中音3
76 {highmedlow}<＇b000000110000 中音3
77 {highmedlow}<＇b000000110000 中音3
78 {highmedlow}<＇b000000110000 中音3
79 {highmedlow}<＇b000000110000 中音3
80 {highmedlow}<＇b000000110000 中音3
81 {highmedlow}<＇b000000110000 中音3
82 {highmedlow}<＇b000000100000 中音2
83 {highmedlow}<＇b000000100000
84 {highmedlow}<＇b000000110000 中音3
85 {highmedlow}<＇b000000110000 中音3
86 {highmedlow}<＇b000000100000 中音2
87 {highmedlow}<＇b000000100000 中音2
88 {highmedlow}<＇b000000010000 中音1
89 {highmedlow}<＇b000000010000 中音1
90 {highmedlow}<＇b000000010000 中音1
91 {highmedlow}<＇b000000010000 中音1
92 {highmedlow}<＇b000000010000 中音1
93 {highmedlow}<＇b000000010000 中音1
94 {highmedlow}<＇b000000010000 中音1
95 {highmedlow}<＇b000000010000 中音1
96 {highmedlow}<＇b000000010000 中音1
97 {highmedlow}<＇b000000010000 中音1
98 {highmedlow}<＇b000000010000 中音1
99 {highmedlow}<＇b000000010000 中音1
100 {highmedlow}<＇b000000010000 中音1
101 {highmedlow}<＇b000000010000 中音1
102 {highmedlow}<＇b000000010000 中音1
103 {highmedlow}<＇b000000010000 中音1
104 {highmedlow}<＇b000000010000 中音1
105 {highmedlow}<＇b000000000110 低音6
106 {highmedlow}<＇b000000000110 低音6
107 {highmedlow}<＇b000000010000 中音1
108 {highmedlow}<＇b000000010000 中音1
109 {highmedlow}<＇b000000100000 中音2
110 {highmedlow}<＇b000000100000 中音2
111 {highmedlow}<＇b000000100000 中音2
112 {highmedlow}<＇b000000100000 中音2
113 {highmedlow}<＇b000000100000 中音2
114 {highmedlow}<＇b000000100000 中音2
115 {highmedlow}<＇b000000110000 中音3
116 {highmedlow}<＇b000000110000
117 {highmedlow}<＇b000000100000 中音2
118 {highmedlow}<＇b000000100000
119 {highmedlow}<＇b000000010000 中音1
120 {highmedlow}<＇b000000010000
121 {highmedlow}<＇b000000000110 低音6
122 {highmedlow}<＇b000000000110
123 {highmedlow}<＇b000000010000 中音1
124 {highmedlow}<＇b000000010000
125 {highmedlow}<＇b000000100000 中音2
126 {highmedlow}<＇b000000100000 中音2
127 {highmedlow}<＇b000000100000 中音2
128 {highmedlow}<＇b000000100000 中音2
129 {highmedlow}<＇b000000100000 中音2
130 {highmedlow}<＇b000000100000 中音2
131 {highmedlow}<＇b000000100000 中音2
132 {highmedlow}<＇b000000100000 中音2
133 {highmedlow}<＇b000000100000 中音2
134 {highmedlow}<＇b000000100000 中音2
135 {highmedlow}<＇b000000100000 中音2
136 {highmedlow}<＇b000000100000 中音2
137 {highmedlow}<＇b000000100000 中音2
138 {highmedlow}<＇b000000100000 中音2
139 {highmedlow}<＇b000000100000 中音2
140 {highmedlow}<＇b000000100000 中音2
141 {highmedlow}<＇b000000110000 中音3
142 {highmedlow}<＇b000000110000 持续2时钟节拍
143 {highmedlow}<＇b000000100000 中音2
144 {highmedlow}<＇b000000100000 持续2时钟节拍
145 {highmedlow}<＇b000000110000 中音3
146 {highmedlow}<＇b000000110000 发10时钟节拍
147 {highmedlow}<＇b000000110000
148 {highmedlow}<＇b000000110000
149 {highmedlow}<＇b000000110000
endcase
end
endmodule 模块结束
7）取码模块源代码顶层模块：
取码模块song模块取数码显示部分位码段码
module quma(highmedlowclk_1mhzdigduan)
input [30] highmedlow
input clk_1mhz
reg[70] dig
output [70]dig定义输出八位位码
reg [70] duan
output [70] duan 定义输出段码代码
always @(posedge clk_1mhz)扫描highmedlow三寄存器值取出位码段码代码
begin
if (high0) 果high值0输出high值
begin dig<8＇b11111011
case (high)
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
else if (med0) 果med值0输出med值
begin dig<8＇b11111101
case (med )
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
else if (low0) 果low值0输出low值
begin dig<8＇b11111110
case (low )
1duan<8＇b00000001
2duan<8＇b00000010
3duan<8＇b00000011
4duan<8＇b00000100
5duan<8＇b00000101
6duan<8＇b00000110
7duan<8＇b00000111
endcase
end
end
endmodule
8）disp：显示模块位输出转换七段数码显示源代码顶层模块：
动态数码显示模块
module disp(duanclk_1khzseg)
input [70]duan
input clk_1khz
output [70]seg
reg [70]seg
always @(posedge clk_1khz)
begin
case(duan)
1seg8＇b11111001
2seg8＇b10100100
3seg8＇b10110000
4seg8＇b10011001
5seg8＇b10010010
6seg8＇b10000010
7seg8＇b11111000
default seg8＇b11111001
endcase
end
endmodule
方案测试
顶层图形文件建立系统进行仿真仿真时输入输出信号频率求先模块进行仿真
1） 48MHz分频成12MHz波形模块仿真波形：
2） 12MHz分频成6MHz波形模块仿真波形：
3）12MHz分频成1MHz波形模块仿真波形：
4）12MHz分频成4Hz波形模块仿真波形：
5）12MHz分频成1khz波形模块仿真波形：
6）音乐发生器模块仿真波形：
7）取码模块仿真波形：
8）显示模块仿真波形：
引脚锁定：
功模块波形仿真通画出原理图仿真完毕接开始引脚锁定：引脚锁定列表表示：
端口名称
引脚位置
端口名称
引脚位置
clk_48mhz
N2
Dig[7]
M4
Speaker
F18
Seg[0]
J8
Dig[0]
L6
Seg[1]
M3
Dig[1]
K5
Seg[2]
K6
Dig[2]
G3
Seg[3]
J6
Dig[3]
G4
Seg[4]
U10
Dig[4]
J3
Seg[5]
N9
Dig[5]
K4
Seg[6]
L10
Dig[6]
L3
Seg[7]
L9
k
L25
引脚锁定载程序：
安装usbblaster驱动程序配置JTAG文件载程序试验箱FPGA芯片中进行调试仿真修改直预期仿真结果
附录：乐曲演奏电路设计原理图生成顶层文件
原理图生成文文件源程序
Copyright (C) 19912006 Altera Corporation
Your Use Of Altera Corporation＇s Design Tools Logic Functions
And Other Software And Tools And Its Ampp Partner Logic
Functions And Any Output Files Any Of The Foregoing
(Including Device Programming Or Simulation Files) And Any
Associated Documentation Or Information Are Expressly Subject
To The Terms And Conditions Of The Altera Program License
Subscription Agreement Altera Megacore Function License
Agreement Or Other Applicable License Agreement Including
Without Limitation That Your Use Is For The Sole Purpose Of
Programming Logic Devices Manufactured By Altera And Sold By
Altera Or Its Authorized Distributors Please Refer To The
Applicable Agreement For Further Details
Module Block1(
Clk_48mhz
Speaker
Dig
Seg
)
Input Clk_48mhz
Output Speaker
Output [70] Dig
Output [70] Seg
Wire Synthesized_Wire_12
Wire Synthesized_Wire_4
Wire [60] Synthesized_Wire_5
Wire Synthesized_Wire_6
Wire Synthesized_Wire_7
Wire Synthesized_Wire_8
Wire [30] Synthesized_Wire_9
Wire [30] Synthesized_Wire_10
Wire [30] Synthesized_Wire_11
Div_Clk12mhz B2v_Inst(Clk_48mhz(Clk_48mhz)
Clk_12mhz(Synthesized_Wire_12))
Div_Clk1khz B2v_Inst1(Clk_12mhz(Synthesized_Wire_12)
Clk_1khz(Synthesized_Wire_4))
Div_Clk1mhz B2v_Inst2(Clk_12mhz(Synthesized_Wire_12)
Clk_1mhz(Synthesized_Wire_8))
Div_Clk4hz B2v_Inst3(Clk_12mhz(Synthesized_Wire_12)
Clk_4hz(Synthesized_Wire_7))
Div_Clk6mhz B2v_Inst4(Clk_12mhz(Synthesized_Wire_12)
Clk_6mhz(Synthesized_Wire_6))
Disp B2v_Inst5(Clk_1khz(Synthesized_Wire_4)
Duan(Synthesized_Wire_5)Seg(Seg))
Song B2v_Inst6(Clk_6mhz(Synthesized_Wire_6)
Clk_4hz(Synthesized_Wire_7)Speaker(Speaker)High(Synthesized_Wire_9)Low(Synthesized_Wire_10)Med(Synthesized_Wire_11))
Quma B2v_Inst9(Clk_1mhz(Synthesized_Wire_8)
High(Synthesized_Wire_9)Low(Synthesized_Wire_10)Med(Synthesized_Wire_11)Dig(Dig)Duan(Synthesized_Wire_5))
Endmodule
实训心
2周实训深刻体会知识匮乏原学理知识通次实理知识升实践程时实践中加深理知识理解外次实仅verilog提高 学许方面知识提高动手力
次实训中遇少问题中12mhz分频4hz时候仿真波形仿真出步步分析发现原设置endtime时间太长想仿真出波形便观察设置10s结果仿真百分49然仿真动调试设置05秒样十分钟仿真仿真波形调试出次编程时候程序综合出现错误song模块中阻塞非阻塞赋值时出现程序中显示模块中开始编写七位二进制阴数码结果硬件测试时候数码显示正常发现数点没赋值数码阳调试修改程序成功高中低音调音节显示出次想编译2首歌switch切换演唱歌曲时组成员研究歌谱例子进行午写出两蝴蝶程序修改song程序成功进行仿真点阵显示歌名时候发现芯片点阵输出引脚3老师分析讲解学会新程序an
通次实仅学知识新认识提高考虑问题分析问题全面性动手操作力培养团队合作精神学致意识做事情规范认真态度综合力提高总课程设计学新知识巩固加深学课理知识程培养综合运知识力思考解决问题力仅加深电子技术课程理解感受设计电路乐趣怕麻烦反复设计绘图修改希次课程设计做说次课程设计非常意义
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