北航电子电路设计数字部分实验报告

电子电路设计数字部分实验报告







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实验 简单组合逻辑设计
实验容
描述综合数较器较数a b相出结果1否出结果0
实验仿真结果

实验代码
程序
module compare(equalab)
input[70] ab
output equal
assign equal(a>b)10
endmodule

测试程序
module t
reg[70] ab
reg clockk
wire equal
initial
begin
a0
b0
clock0
k0
end
always #50 clock ~clock
always @ (posedge clock)
begin
a[0]{random}2
a[1]{random}2
a[2]{random}2
a[3]{random}2
a[4]{random}2
a[5]{random}2
a[6]{random}2
a[7]{random}2
b[0]{random}2
b[1]{random}2
b[2]{random}2
b[3]{random}2
b[4]{random}2
b[5]{random}2
b[6]{random}2
b[7]{random}2
end
initial
begin #100000 stopend
compare m(equal(equal)a(a)b(b))
endmodule
实验二 简单分频时序逻辑电路设计
实验容
always块@(posedge clk)@(negedge clk)结构表述12分频器综合模型观察时序仿真结果
实验仿真结果

实验代码
程序
module half_clk(resetclk_inclk_out)
input clk_inreset
output clk_out
reg clk_out

always@(negedge clk_in)
begin
if(reset)
clk_out0
else
clk_out~clk_out
end
endmodule

测试程序
`timescale 1ns100ps
`define clk_cycle 50
module top
reg clkreset
wire clk_out

always #`clk_cycle clk~clk

initial
begin
clk0
reset1
#10 reset0
#110 reset1
#100000 stop
end

half_clk m0(reset(reset)clk_in(clk)clk_out(clk_out))
endmodule
实验三 利条件语句实现计数分频时序电路
实验容
利10MHz时钟设计单周期形状周期波形
实验仿真结果

实验代码
程序
module fdivision(RESETF10Mout)
input F10MRESET
output out
reg out
reg[70] i
always @(posedge F10M)
if(RESET)
begin
out<0
i<0
end
else if(i2||i3)
begin
out~out
i end
else if(i5)
i<1
else
i endmodule

测试程序
`timescale 1ns100ps

module division_top
reg F10MRESET
wire out
always #50 F10M~F10M
initial
begin
RESET1
F10M0
#90 RESET0
#100 RESET1
#10000 stop
end
fdivision fdivision(RESET(RESET)F10M(F10M)out(out))
endmodule
实验四 阻塞赋值非阻塞赋值区
实验容
较四种写法观察阻塞非阻塞赋值区
Blocking：
always @(posedge clk)
begin
ba
cb
end

Blocking1：
always @(posedge clk)
begin
cb
ba
end

Blocking2：
always @(posedge clk) ba
always @(posedge clk) cb

non_Blocking：
always@(posedge clk)
begin
b c End
实验仿真结果

实验代码
程序
module blocking(clkabc)
output[30] bc
input[30] a
input clk
reg[30] bc
always @(posedge clk)
begin
ba
cb
end
endmodule

测试部分
`timescale 1 ns100 ps
`include blockingv
`include blocking1v
`include blocking2v
`include non_blockingv

module compareTop
wire[30]b11c11b12c12b13c13b2c2
reg[30]a
reg clk
initial
begin
clk0
forever#50 clk~clk
end
initial
begin
a4＇h3
display(da)
#100 a4＇h7
display(da)
#100 a4＇hf
display(da)
#100 a4＇ha
display(da)
#100 a4＇h2
display(da)
#100 stop
end
blocking blocking(clkab11c11)
blocking1 blocking1(clkab12c12)
blocking2 blocking2(clkab13c13)
non_blocking non_blocking(clkab2c2)
endmodule
实验五 always块实现较复杂组合逻辑
实验目
运always块设计8路数选择器求：路输入数输出数均4位2进制数选择开关（少3位）输入数发生变化时输出数相应变化
实验仿真结果

实验代码
程序
module alu(outopcodea1a2a3a4a5a6a7a8)
output[30] out
reg[30] out
input[30] a0a1a2a3a4a5a6a7
input[20] opcode
always@(opcode or a1 or a2 or a3 or a4 or a5 or a6 or a7 or a0)
begin
case(opcode)
3＇d0 outa0
3＇d1 outa1
3＇d2 outa2
3＇d3 outa3
3＇d4 outa4
3＇d5 outa5
3＇d6 outa6
3＇d7 outa7
defaultout4＇b0000
endcase
end
endmodule

测试程序
`timescale 1ns1ns
`include main5v
module alutext
wire[30] out
reg[30] a1a2a3a4a5a6a7a8
reg[20] opcode
initial
begin
a1{random}16
a2{random}16
a3{random}16
a4{random}16
a5{random}16
a6{random}16
a7{random}16
a8{random}16
repeat(100)
begin
#100 opcode{random}8
a1{random}16
a2{random}16
a3{random}16
a4{random}16
a5{random}16
a6{random}16
a7{random}16
a8{random}16
end
#100 stop
end
alu alu(outopcodea1a2a3a4a5a6a7a8)
endmodule

实验六 Verilog HDL中函数
实验目
设计带控制端逻辑运算电路分完成正整数方立方数5阶运算
实验仿真结果

实验代码
程序
module tryfunct(clknresult1result2result3reset)
output[310]result1result2result3
input[30]n
input resetclk
reg[310]result1result2result3
always@(posedge clk)
begin
if(reset)
begin
result1<0
result2<0
result3<0
end
else
begin
result1 result2 result3 end
end

function[310]fun1
input[30]operand
fun1operand*operand
endfunction

function[310]fun2
input[30]operand
begin
fun2operand*operand
fun2operand*fun2
end
endfunction

function[310]fun3
input[30]operand
reg[30]index
begin
fun31
if(operand<11)
for(index2index fun3index*fun3
else
for(index2index<10indexindex+1)
fun3index*fun3
end
endfunction

endmodule

测试程序
`includemain6v
`timescale 1ns100ps
module tryfunctTop
reg[30] ni
reg resetclk
wire[310]result1result2result3
initial
begin
clk0
n0
reset1
#100 reset0
#100 reset1
for(i0i<15ii+1)
begin
#200 ni
end
#100 stop
end
always#50 clk~clk
tryfunct m(clk(clk)n(n)result1(result1)result2(result2)result3(result3)reset(reset))
endmodule
实验七 Verilog HDL中务(task)
实验目
两种方法设计功相模块该模块完成四8位2进制输入数泡排序第种模仿原题例子中纯组合逻辑实现第二种假设8位数时钟节拍串行输入求时钟触发务执行法时钟周期完成次数交换操作
实验仿真结果


实验代码
程序1
module rank(rarbrcrdabcd)
output[70]rarbrcrd
input[70]abcd
reg[70]rarbrcrdvavbvcvdtmp
reg i
always@(a or b or c or d)
begin
{vavbvcvd}{abcd}
repeat(7)
begin
exchange(vavb)
exchange(vbvc)
exchange(vcvd)
end
{rarbrcrd}{vavbvcvd}
end

task exchange
inout[70] xy
reg[70] tmp
if(x>y)
begin
tmpx
xy
ytmp
end
endtask
endmodule

测试部分1
`timescale 1ns100ps
`include main7v
module task_Top
reg[70]abcd
wire[70]rarbrcrd
initial
begin
a0b0c0d0
repeat(50)
begin
#100 a{random}255
b{random}255
c{random}255
d{random}255
end
#100 stop
end
rank rank(ra(ra)rb(rb)rc(rc)rd(rd)a(a)b(b)c(c)d(d))
endmodule

程序2
module rank(arstclkrarbrcrd)
output[70]rarbrcrd
input[70]a
input clkrst
reg[70]rarbrcrd
reg[70]vavbvcvd
reg[30]i

always@(posedge clk or negedge clk)
begin
if(rst)
begin
va0
vb0
vc0
vd0
i0
end
else
begin
if(i<8)
begin
ii+1
vaa
exchange(vavb)
exchange(vbvc)
exchange(vcvd)
exchange(vavb)
exchange(vbvc)
exchange(vavb)
{rarbrcrd}{vavbvcvd}
end
end
end


task exchange
inout[70] xy
reg[70] tmp
if(x>y)
begin
tmpx
xy
ytmp
end
endtask

endmodule

测试部分2
`timescale 1ns100ps
`include main7_otherv
module task_Top
reg[70]a
wire[70]rarbrcrd
reg clkrst



initial
begin
a0
rst0
clk0
#50 rst1
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 a{8{random}}
#100 stop
end
always #100 clk~clk

rank rank(a(a)rst(rst)clk(clk)ra(ra)rb(rb)rc(rc)rd(rd))
endmodule
实验八 利限状态机进行时序逻辑设计
实验目
设计串行数检测器求连续四四1 时输出1输入情况0
实验仿真结果

实验代码
程序
module seqdet(xzclkrststate)
input xclkrst
output z
output[20] state
reg[20] state
wire z
parameter IDLE＇d0A＇d1B＇d2C＇d3D＇d4

assign z(stateD&&x1)10

always@(posedge clk)
if(rst)
begin
state end
else
casex(state)
IDLE
if(x1)
begin
state end
A
if(x1)
begin
state end
else
begin
state end
B
if(x1)
begin
state end
else
begin
state end
C
if(x1)
begin
state end
else
begin
state end
D
if(x1)
begin
state end
else
begin
state end
defaultstateIDLE
endcase
endmodule

测试代码
`include main8v
module seqdet_Top
reg clkrst
reg[230] data
wire[20] state
wire zx

assign xdata[23]

always #10 clk~clk

always@(posedge clk)
data{data[220]data[23]}

initial
begin
clk0
rst1
#2 rst0
#30 rst1
data＇b1001_1111_0111_1110
#500 stop
end
seqdet m(xzclkrststate)
endmodule

实验九 楼梯灯
实验目
Ø 楼楼次3感应灯：灯1灯2灯3行楼梯时灯感应动点亮8s感应信号消失点亮8s感应信号存时间超8s感应信号消失4s灯动关闭
Ø 务1：做出逻辑电路设计仿真
Ø 务2：考虑抖情况感应信号达存毛刺(05s)设计合适逻辑剔出
务3：节约源灯点亮时动关闭灯做出逻辑设计仿真（仅考虑情况）
实验仿真结果

实验代码
程序
module light_All(clk10rstswitchlight)

input clk10rst
input[20]switch
output[20]light

reg[20]state1state2state3
reg[70]count1count2count3
reg[20]count_1count_2count_3
reg[20]light

parameter
state1_start3＇b000state2_start3＇b000state3_start3＇b000
state1_work3＇b001state2_work3＇b001state3_work3＇b001
state1_up3＇b010state2_up3＇b010state3_up3＇b010
state1_down3＇b011state2_down3＇b011state3_down3＇b011
state1_other3＇b100state2_other3＇b100state3_other3＇b100

always@(posedge clk10)
if(rst)
begin
state1 count1<8＇b0
count_1<3＇b0
end
else
if(switch[0]＇b1&&count_1<4)
count_1 else
case(state1)

state1_start
if(switch[0]＇b1)
begin
state1 count1<78
end
else
begin
state1 light[0]<＇b0
end

state1_work
if(count1>0)
begin
count1 if(switch[0]＇b0&&(state23＇b010||state33＇b010))
begin
light[0]<＇b0
state1 end
end
else
if(switch[0]＇b0)
begin
state1 end
else
begin
state1 count1<39
end

state1_other
if(switch[0]＇b1)
state1 else
if(count1>0)
begin
count1 if(switch[0]＇b0&&(state23＇b010||state33＇b010))
begin
light[0]<＇b0
state1 end
end
else
state1

state1_down
begin
light[0]<＇b0
count_1<3＇b0
state1 end

state1_up
begin
light[0]<＇b1
state1 end

default
state1
endcase

always@(posedge clk10)
if(rst)
begin
state2 count2<8＇b0
count_2<3＇b0
end
else
if(switch[1]＇b1&&count_2<4)
count_2 else
case(state2)

state2_start
if(switch[1]＇b1)
begin
state2 count2<78
end
else
begin
state2 light[1]<＇b0
end

state2_work
if(count2>0)
begin
count2 if(switch[1]＇b0&&(state13＇b010||state33＇b010))
begin
light[1]<＇b0
state2 end
end
else
if(switch[1]＇b0)
begin
state2 end
else
begin
state2 count2<39
end

state2_other
if(switch[1]＇b1)
state2 else
if(count2>0)
begin
count2 if(switch[1]＇b0&&(state13＇b010||state33＇b010))
begin
light[1]<＇b0
state2 end
end
else
state2
state2_down
begin
light[1]<＇b0
count_2<3＇b0
state2 end

state2_up
begin
light[1]<＇b1
state2 end

default
state2
endcase

always@(posedge clk10)
if(rst)
begin
state3 count3<8＇b0
count_3<3＇b0
end
else
if(switch[2]＇b1&&count_3<4)
count_3 else
case(state3)

state3_start
if(switch[2]＇b1)
begin
state3 count3<78
end
else
begin
state3 light[2]<＇b0
end

state3_work
if(count3>0)
begin
count3 if(switch[2]＇b0&&(state13＇b010||state23＇b010))
begin
light[2]<＇b0
state3 end
end
else
if(switch[2]＇b0)
begin
state3 end
else
begin
state3 count3<39
end

state3_other
if(switch[2]＇b1)
state3 else
if(count3>0)
begin
count3 if(switch[2]＇b0&&(state13＇b010||state23＇b010))
begin
light[2]<＇b0
state3 end
end
else
state3
state3_down
begin
light[2]<＇b0
count_3<3＇b0
state3 end

state3_up
begin
light[2]<＇b1
state3 end

default
state3
endcase

endmodule

测试程序
`timescale 100ns10ns
module test_light_All
reg clk10rst
reg[20] updown
wire[20] swh
wire[20] light

parameter HALF_PERIOD 5

always #HALF_PERIOD clk10~clk10

initial
begin
clk10 0
rst 1
up 3＇b000down 3＇b000
#1 rst 0
#10 rst 1
#100 up 3＇b001 down 3＇b000
#500 up 3＇b010 down 3＇b100
#600 up 3＇b011 down 3＇b010
#30 up 3＇b010
#80 up 3＇b011
#900 up 3＇b010 down 3＇b001
#500 up 3＇b101 down 3＇b001
#600 up 3＇b000 down 3＇b101
#80 down 3＇b111
#30 down 3＇b101
#100 up 3＇b011 down 3＇b010
#500 up 3＇b100 down 3＇b101
#500 up 3＇b101 down 3＇b000
#600 up 3＇b010 down 3＇b110
#100 up 3＇b111 down 3＇b001
#200 up 3＇b000 down 3＇b000
#1000 stop
end

assign swh up | down

light_All m5(clk10rstswhlight)
endmodule

总结
通Verilog实验理解示范实验中条语句然进行功仿真加深Verilog理解老师课堂讲知识点更加深入解解决课堂学中解决问题阻塞赋值非阻塞赋值实验更加清楚明白解阻塞赋值非阻塞赋值区避免课堂讲解难理解时加深知识点记忆通做实验掌握基组合逻辑电路实现方法生成方法掌握测试模块编写方法掌握种语句时序模块设计中解Verilog语言中实现方法区阻塞赋值非阻塞赋值区assignalways两种组合电路实现方法区学测试模块编写综合层次仿真通综合布局布线解层次仿真物理意义更加完整解Verilog更加深刻解学知识学够设计较简单程序实现预期功
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