基FPGA数字系统设计
作业
学号：
姓名：
班级：
题目：设计Parwan control section 部状态机s1＼s2＼＼s9＼出功仿真？
题目二：利分层结构设计ParwanCPU出功仿真 （利实验课中出TESTBENCH）
实验原理图
Control Section Structure：s1…s9（图示）
Inputs and outputs of PARWAN control sections
–Applied to categories signal name functions
实验程
11 创建工程
（1） 开ISE13x软件选择File>New Project弹出话框中输入工程名路径
（2） 单击步选择芯片Spartan3E开发板芯片型号Spartan3E XC3S500E芯片FG320封装
（3） 单击Next进入工程信息页面确认误点击Finish完成工程创建
12 测试文件
(1) 选择菜单栏中Project>New Source
(2) Select Source Type窗口中选择左侧VHDL Test Bench右侧File Name栏中输入文件名par_control_unit_tb
(3) 单击Next钮选择关联文件
13 实验截图
实验代码
实现程中定义CPU信号接口外设置输出类型接口名字present_state_value调试仿真程中输出CPU处状态便调试分析
整状态机实现程case … IS … when 逻辑结构present_state next_state两状态变量详细实现代码示：
LIBRARY IEEE
USE IEEEstd_logic_1164ALL
USE worksynthesis_utilitiesALL
ENTITY par_control_unit IS
PORT (clk IN std_logic
register control signals
load_ac zero_ac
load_ir
increment_pc load_page_pc load_offset_pc reset_pc
load_page_mar load_offset_mar
load_sr cm_carry_sr
bus connection control signals
pc_on_mar_page_bus ir_on_mar_page_bus
pc_on_mar_offset_bus dbus_on_mar_offset_bus
pc_offset_on_dbus obus_on_dbus databus_on_dbus
mar_on_adbus
dbus_on_databus
logic unit function control outputs
arith_shift_left arith_shift_right OUT std_logic
alu_andalu_notalu_aalu_addalu_balu_sub out std_logic
inputs from the data section
ir_lines IN std_logic_vector (7 DOWNTO 0)
status IN std_logic_vector (3 DOWNTO 0)
memory control and other external signals
read_mem write_mem OUT std_logic interrupt IN std_logic
test
present_state_value out std_logic_vector (3 DOWNTO 0)
)
END par_control_unit
ARCHITECTURE dataflow_synthesizable OF par_control_unit IS
TYPE cpu_states IS (s1s2s3s4s5s6s7s8s9)
SIGNAL present_state next_state cpu_states
SIGNAL next_state_value std_logic_vector (3 DOWNTO 0)
BEGIN
clocking PROCESS (clk interrupt)
BEGIN
IF (interrupt ＇1＇) THEN
present_state < s1
present_state_value <0001
ELSIF clk＇EVENT AND clk ＇0＇ THEN
present_state < next_state
present_state_value END IF
END PROCESS clocking
sequencing PROCESS ( present_state ir_lines status
interrupt)
BEGIN
load_ac < ＇0＇ zero_ac < ＇0＇ load_ir < ＇0＇
increment_pc < ＇0＇
load_page_pc < ＇0＇ load_offset_pc < ＇0＇ reset_pc
< ＇0＇
load_page_mar < ＇0＇ load_offset_mar < ＇0＇
load_sr < ＇0＇ cm_carry_sr < ＇0＇
bus connection control signals
pc_on_mar_page_bus < ＇0＇ ir_on_mar_page_bus < ＇0＇
pc_on_mar_offset_bus < ＇0＇ dbus_on_mar_offset_bus <
＇0＇
pc_offset_on_dbus < ＇0＇ obus_on_dbus < ＇0＇
databus_on_dbus < ＇0＇
mar_on_adbus < ＇0＇ dbus_on_databus < ＇0＇
logic unit function control outputs
arith_shift_left < ＇0＇ arith_shift_right < ＇0＇
alu_and <＇0＇alu_not <＇0＇alu_a <＇0＇alu_add <＇0＇alu_b <＇0＇alu_sub <＇0＇
memory control and other external signals
read_mem < ＇0＇ write_mem < ＇0＇
CASE present_state IS
WHEN s1 >
1
IF (interrupt ＇1＇) THEN
reset_pc < ＇1＇
next_state < s1
next_state_value <0001
ELSE
pc_on_mar_page_bus < ＇1＇
pc_on_mar_offset_bus < ＇1＇
load_page_mar < ＇1＇
load_offset_mar < ＇1＇
next_state < s2
next_state_value <0010
END IF
WHEN s2 >
2
read memory into ir
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
alu_a < ＇1＇
load_ir < ＇1＇
increment_pc < ＇1＇
next_state < s3
next_state_value <0011
WHEN s3 >
3
pc_on_mar_page_bus < ＇1＇
pc_on_mar_offset_bus < ＇1＇
load_page_mar < ＇1＇
load_offset_mar < ＇1＇
IF (ir_lines (7 DOWNTO 4) 1110) THEN
next_state < s4
next_state_value <0100
ELSE
CASE ir_lines (3 DOWNTO 0) IS
WHEN 0001 > cla
zero_ac < ＇1＇
load_ac < ＇1＇
WHEN 0100 > cmc
cm_carry_sr < ＇1＇
WHEN 1000 > asl
alu_b < ＇1＇
arith_shift_left < ＇1＇
load_sr < ＇1＇
load_ac < ＇1＇
WHEN 1001 > asr
alu_b < ＇1＇
arith_shift_right < ＇1＇
load_sr < ＇1＇
load_ac < ＇1＇
WHEN OTHERS > NULL
END CASE
next_state < s2
next_state_value <0010
END IF
WHEN s4 >
4
read memory into mar offset
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
dbus_on_mar_offset_bus < ＇1＇
load_offset_mar < ＇1＇
IF ( ir_lines (7 DOWNTO 6) 11 ) THEN
ir_on_mar_page_bus < ＇1＇
load_page_mar < ＇1＇
IF ( ir_lines (4) ＇1＇ )
THEN
next_state < s5
next_state_value <0101
ELSE
next_state < s6
next_state_value <0110
END IF
ELSE jsr or bra do not alter mar
page
IF ( ir_lines (5) ＇0＇ ) THEN
jsr
next_state < s7
next_state_value <0111
ELSE
next_state < s9
next_state_value <1001
END IF
END IF
increment_pc < ＇1＇
WHEN s5 >
5
read actual operand from memory into mar
offset
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
dbus_on_mar_offset_bus < ＇1＇
load_offset_mar < ＇1＇
next_state < s6
next_state_value <0110
WHEN s6 >
6
IF ( ir_lines (7 DOWNTO 5) 100 ) THEN jmp
load_page_pc < ＇1＇
load_offset_pc < ＇1＇
next_state < s2
next_state_value <0010
ELSIF ( ir_lines (7 DOWNTO 5) 101 ) THEN
mar on adbus ac on databus write
to memory
mar_on_adbus < ＇1＇
alu_b< ＇1＇
obus_on_dbus < ＇1＇
dbus_on_databus < ＇1＇
write_mem < ＇1＇
next_state < s1
next_state_value <0001
ELSIF ( ir_lines (7) ＇0＇ ) THEN
lda and add sub
mar on adbus read memory for
operand perform operation
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
IF ( ir_lines (6) ＇0＇ ) THEN
lda and
IF ( ir_lines (5) ＇0＇ )
THEN lda
alu_a< ＇1＇
ELSE and
alu_and< ＇1＇
END IF
ELSE add sub
IF ( ir_lines (5) ＇0＇ )
THEN add
alu_add< ＇1＇
ELSE sub
alu_sub< ＇1＇
END IF
END IF
load_sr < ＇1＇
load_ac < ＇1＇
next_state < s1
next_state_value <0001
END IF
WHEN s7 >
7
write pc offset to top of subroutine
mar_on_adbus < ＇1＇
pc_offset_on_dbus < ＇1＇
dbus_on_databus < ＇1＇
write_mem < ＇1＇
load_offset_pc < ＇1＇
next_state < s8
next_state_value <1000
WHEN s8 >
8
increment_pc < ＇1＇
next_state < s1
next_state_value <0001
WHEN s9 >
9
IF ( all_or (status AND ir_lines (3 DOWNTO 0)) ＇1＇) THEN
load_offset_pc < ＇1＇
END IF
next_state < s1
next_state_value <0001
实验原理
实验程
21 创建工程
（1） 开ISE13x软件选择File>New Project弹出话框中输入工程名路径
（2） 单击步选择芯片Spartan3E开发板芯片型号Spartan3E XC3S500E芯片FG320封装
（3） 单击Next进入工程信息页面确认误点击Finish完成工程创建
22 设计输入
选择Project>Add copy of source实验源代码添加工程中
23 综合实现
（1） 编写汇编测试代码
（2）文编辑器开实验源代码中simpleasm文件
（3）测试代码转换存文件
（4）编译执行程序
24 设计仿真
25 结果截图
编写testbench代码状态机进行功仿真Testbench核心代码：
stim_proc process
begin
hold reset state for 100 ns
wait for 10 ns
ir_lines < 01101111 SUB loc
wait for clk_period*10
ir_lines < 10001111 JMP loc
wait for clk_period*10
ir_lines < 10101111 STA loc
wait for clk_period*10
ir_lines < 11111000 BRA_V_addr
wait for clk_period*10
ir_lines < 11100001 CLA
wait for clk_period*10
end process
代码见测试波形中选取4种ir_line值测试面选择两处仿真波形进行分析：
图51 STA loc 仿真波形图
STA loc 仿真波形图中连续时钟周期里ir_line值10101111知该指令STA 1111结合parwan状态转换关系开始CPU处s1状态interrupt0’转s2状态转s3状态ir_line（7to4）1110转s4状态ir_line（7to4）11X0转s6状态ir_line（7to5）1010转回s1完成次循环周期相应状态相应信号会设1s1中信号load_page_marload_offset_marpc_on_mar_page_buspc_on_mar_offset_bus等信号1状态机设计相符
图52 CLA 仿真波形图
CLA 仿真波形图中黄线部分开始时钟周期ir_line值11100001parwan指令集知指令CLA结合parwan状态设计开始CPU处s1状态interrupt0’转s2状态转s3状态ir_line（7to4）1110转s2状态s2s3中循环验证程序正确性
实验总结：次作业前四次机基础通利机实验力部分实验代码进行次Parwan CPU设计基说次作业机更难度首先进行次综合性实验次机时均出实验步骤否认次实验更提高Parwan CPU理解提高实验力更帮助
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基FPGA数字系统设计
作业
学号：
姓名：
班级：
题目：设计Parwan control section 部状态机s1＼s2＼＼s9＼出功仿真？
题目二：利分层结构设计ParwanCPU出功仿真 （利实验课中出TESTBENCH）
实验原理图
Control Section Structure：s1…s9（图示）
Inputs and outputs of PARWAN control sections
–Applied to categories signal name functions
实验程
11 创建工程
（1） 开ISE13x软件选择File>New Project弹出话框中输入工程名路径
（2） 单击步选择芯片Spartan3E开发板芯片型号Spartan3E XC3S500E芯片FG320封装
（3） 单击Next进入工程信息页面确认误点击Finish完成工程创建
12 测试文件
(1) 选择菜单栏中Project>New Source
(2) Select Source Type窗口中选择左侧VHDL Test Bench右侧File Name栏中输入文件名par_control_unit_tb
(3) 单击Next钮选择关联文件
13 实验截图
实验代码
实现程中定义CPU信号接口外设置输出类型接口名字present_state_value调试仿真程中输出CPU处状态便调试分析
整状态机实现程case … IS … when 逻辑结构present_state next_state两状态变量详细实现代码示：
LIBRARY IEEE
USE IEEEstd_logic_1164ALL
USE worksynthesis_utilitiesALL
ENTITY par_control_unit IS
PORT (clk IN std_logic
register control signals
load_ac zero_ac
load_ir
increment_pc load_page_pc load_offset_pc reset_pc
load_page_mar load_offset_mar
load_sr cm_carry_sr
bus connection control signals
pc_on_mar_page_bus ir_on_mar_page_bus
pc_on_mar_offset_bus dbus_on_mar_offset_bus
pc_offset_on_dbus obus_on_dbus databus_on_dbus
mar_on_adbus
dbus_on_databus
logic unit function control outputs
arith_shift_left arith_shift_right OUT std_logic
alu_andalu_notalu_aalu_addalu_balu_sub out std_logic
inputs from the data section
ir_lines IN std_logic_vector (7 DOWNTO 0)
status IN std_logic_vector (3 DOWNTO 0)
memory control and other external signals
read_mem write_mem OUT std_logic interrupt IN std_logic
test
present_state_value out std_logic_vector (3 DOWNTO 0)
)
END par_control_unit
ARCHITECTURE dataflow_synthesizable OF par_control_unit IS
TYPE cpu_states IS (s1s2s3s4s5s6s7s8s9)
SIGNAL present_state next_state cpu_states
SIGNAL next_state_value std_logic_vector (3 DOWNTO 0)
BEGIN
clocking PROCESS (clk interrupt)
BEGIN
IF (interrupt ＇1＇) THEN
present_state < s1
present_state_value <0001
ELSIF clk＇EVENT AND clk ＇0＇ THEN
present_state < next_state
present_state_value
END PROCESS clocking
sequencing PROCESS ( present_state ir_lines status
interrupt)
BEGIN
load_ac < ＇0＇ zero_ac < ＇0＇ load_ir < ＇0＇
increment_pc < ＇0＇
load_page_pc < ＇0＇ load_offset_pc < ＇0＇ reset_pc
< ＇0＇
load_page_mar < ＇0＇ load_offset_mar < ＇0＇
load_sr < ＇0＇ cm_carry_sr < ＇0＇
bus connection control signals
pc_on_mar_page_bus < ＇0＇ ir_on_mar_page_bus < ＇0＇
pc_on_mar_offset_bus < ＇0＇ dbus_on_mar_offset_bus <
＇0＇
pc_offset_on_dbus < ＇0＇ obus_on_dbus < ＇0＇
databus_on_dbus < ＇0＇
mar_on_adbus < ＇0＇ dbus_on_databus < ＇0＇
logic unit function control outputs
arith_shift_left < ＇0＇ arith_shift_right < ＇0＇
alu_and <＇0＇alu_not <＇0＇alu_a <＇0＇alu_add <＇0＇alu_b <＇0＇alu_sub <＇0＇
memory control and other external signals
read_mem < ＇0＇ write_mem < ＇0＇
CASE present_state IS
WHEN s1 >
1
IF (interrupt ＇1＇) THEN
reset_pc < ＇1＇
next_state < s1
next_state_value <0001
ELSE
pc_on_mar_page_bus < ＇1＇
pc_on_mar_offset_bus < ＇1＇
load_page_mar < ＇1＇
load_offset_mar < ＇1＇
next_state < s2
next_state_value <0010
END IF
WHEN s2 >
2
read memory into ir
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
alu_a < ＇1＇
load_ir < ＇1＇
increment_pc < ＇1＇
next_state < s3
next_state_value <0011
WHEN s3 >
3
pc_on_mar_page_bus < ＇1＇
pc_on_mar_offset_bus < ＇1＇
load_page_mar < ＇1＇
load_offset_mar < ＇1＇
IF (ir_lines (7 DOWNTO 4) 1110) THEN
next_state < s4
next_state_value <0100
ELSE
CASE ir_lines (3 DOWNTO 0) IS
WHEN 0001 > cla
zero_ac < ＇1＇
load_ac < ＇1＇
WHEN 0100 > cmc
cm_carry_sr < ＇1＇
WHEN 1000 > asl
alu_b < ＇1＇
arith_shift_left < ＇1＇
load_sr < ＇1＇
load_ac < ＇1＇
WHEN 1001 > asr
alu_b < ＇1＇
arith_shift_right < ＇1＇
load_sr < ＇1＇
load_ac < ＇1＇
WHEN OTHERS > NULL
END CASE
next_state < s2
next_state_value <0010
END IF
WHEN s4 >
4
read memory into mar offset
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
dbus_on_mar_offset_bus < ＇1＇
load_offset_mar < ＇1＇
IF ( ir_lines (7 DOWNTO 6) 11 ) THEN
ir_on_mar_page_bus < ＇1＇
load_page_mar < ＇1＇
IF ( ir_lines (4) ＇1＇ )
THEN
next_state < s5
next_state_value <0101
ELSE
next_state < s6
next_state_value <0110
END IF
ELSE jsr or bra do not alter mar
page
IF ( ir_lines (5) ＇0＇ ) THEN
jsr
next_state < s7
next_state_value <0111
ELSE
next_state < s9
next_state_value <1001
END IF
END IF
increment_pc < ＇1＇
WHEN s5 >
5
read actual operand from memory into mar
offset
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
dbus_on_mar_offset_bus < ＇1＇
load_offset_mar < ＇1＇
next_state < s6
next_state_value <0110
WHEN s6 >
6
IF ( ir_lines (7 DOWNTO 5) 100 ) THEN jmp
load_page_pc < ＇1＇
load_offset_pc < ＇1＇
next_state < s2
next_state_value <0010
ELSIF ( ir_lines (7 DOWNTO 5) 101 ) THEN
mar on adbus ac on databus write
to memory
mar_on_adbus < ＇1＇
alu_b< ＇1＇
obus_on_dbus < ＇1＇
dbus_on_databus < ＇1＇
write_mem < ＇1＇
next_state < s1
next_state_value <0001
ELSIF ( ir_lines (7) ＇0＇ ) THEN
lda and add sub
mar on adbus read memory for
operand perform operation
mar_on_adbus < ＇1＇
read_mem < ＇1＇
databus_on_dbus < ＇1＇
IF ( ir_lines (6) ＇0＇ ) THEN
lda and
IF ( ir_lines (5) ＇0＇ )
THEN lda
alu_a< ＇1＇
ELSE and
alu_and< ＇1＇
END IF
ELSE add sub
IF ( ir_lines (5) ＇0＇ )
THEN add
alu_add< ＇1＇
ELSE sub
alu_sub< ＇1＇
END IF
END IF
load_sr < ＇1＇
load_ac < ＇1＇
next_state < s1
next_state_value <0001
END IF
WHEN s7 >
7
write pc offset to top of subroutine
mar_on_adbus < ＇1＇
pc_offset_on_dbus < ＇1＇
dbus_on_databus < ＇1＇
write_mem < ＇1＇
load_offset_pc < ＇1＇
next_state < s8
next_state_value <1000
WHEN s8 >
8
increment_pc < ＇1＇
next_state < s1
next_state_value <0001
WHEN s9 >
9
IF ( all_or (status AND ir_lines (3 DOWNTO 0)) ＇1＇) THEN
load_offset_pc < ＇1＇
END IF
next_state < s1
next_state_value <0001
实验原理
实验程
21 创建工程
（1） 开ISE13x软件选择File>New Project弹出话框中输入工程名路径
（2） 单击步选择芯片Spartan3E开发板芯片型号Spartan3E XC3S500E芯片FG320封装
（3） 单击Next进入工程信息页面确认误点击Finish完成工程创建
22 设计输入
选择Project>Add copy of source实验源代码添加工程中
23 综合实现
（1） 编写汇编测试代码
（2）文编辑器开实验源代码中simpleasm文件
（3）测试代码转换存文件
（4）编译执行程序
24 设计仿真
25 结果截图
编写testbench代码状态机进行功仿真Testbench核心代码：
stim_proc process
begin
hold reset state for 100 ns
wait for 10 ns
ir_lines < 01101111 SUB loc
wait for clk_period*10
ir_lines < 10001111 JMP loc
wait for clk_period*10
ir_lines < 10101111 STA loc
wait for clk_period*10
ir_lines < 11111000 BRA_V_addr
wait for clk_period*10
ir_lines < 11100001 CLA
wait for clk_period*10
end process
代码见测试波形中选取4种ir_line值测试面选择两处仿真波形进行分析：
图51 STA loc 仿真波形图
STA loc 仿真波形图中连续时钟周期里ir_line值10101111知该指令STA 1111结合parwan状态转换关系开始CPU处s1状态interrupt0’转s2状态转s3状态ir_line（7to4）1110转s4状态ir_line（7to4）11X0转s6状态ir_line（7to5）1010转回s1完成次循环周期相应状态相应信号会设1s1中信号load_page_marload_offset_marpc_on_mar_page_buspc_on_mar_offset_bus等信号1状态机设计相符
图52 CLA 仿真波形图
CLA 仿真波形图中黄线部分开始时钟周期ir_line值11100001parwan指令集知指令CLA结合parwan状态设计开始CPU处s1状态interrupt0’转s2状态转s3状态ir_line（7to4）1110转s2状态s2s3中循环验证程序正确性
实验总结：次作业前四次机基础通利机实验力部分实验代码进行次Parwan CPU设计基说次作业机更难度首先进行次综合性实验次机时均出实验步骤否认次实验更提高Parwan CPU理解提高实验力更帮助
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